Conventional timing extractors used in optical disk playback devices and the like include a feedback timing extractor described in Patent Document 1, for example. In this feedback timing extractor, as shown in a block structure in FIG. 20, an input playback signal is quantized by an A/D converter 1, and, based on the quantized data provided through an offset correction section 8, a phase frequency comparator 13 calculates a frequency error and a phase error. Then, the amount of the digital correction obtained, which is provided by way of a loop filter 14, is converted into an analog value by a D/A converter (not shown), so that the oscillation frequency of a VCO (a voltage controlled oscillator) 15 is controlled. By performing this feedback control, synchronization is achieved between a clock for driving the A/D converter 1 and the digital sections 8, 13, and 14 and the playback signal. For the data decoding, decoding processing can be performed based on the quantized data, because the clock and the quantized data are synchronized with each other.
On the other hand, a feedforward timing extraction circuit which uses a frequency synthesizer operating at a fixed rate is discussed in Patent Document 2. FIG. 21 illustrates a block structure in the feedforward timing extractor. This feedforward system uses an A/D converter 1 which quantizes a playback signal in accordance with a constant cycle (fixed rate) clock generated and output by a constant clock oscillator 18. Based on the digital data sequence quantized by the A/D converter 1 and on the fixed rate clock, a synchronous clock arithmetic circuit 17 estimates the edge positions of a synchronous clock, and an interpolation circuit 16 performs interpolation processing on the quantized data, while pulses of the fixed rate clock are eliminated to generate a pseudo-synchronous clock Data CLK. The quantized data obtained after the interpolation processing and the pseudo-synchronous clock Data CLK are used to perform decoding process.
In the conventional feedback structure described in Patent Document 1, if high-speed playback is necessary, the digital circuits need pipeline registers for timing compensation, which results in increase in clock latency. Thus, the feedback structure has a problem in that the stability of the loop deteriorates easily.
In contrast to this, in the feedforward control, the amount of correction is calculated from the quantized data sequence, and the correction processing is performed on the already quantized data sequence. The feedforward control thus has the advantage of being free from the influence of clock latency, and is suitable for high-speed playback.    Patent Document 1: Japanese Laid-Open Publication No. 2002-8315    Patent Document 2: Japanese Laid-Open Publication No. 8-161829